Integrated circuit (IC) chips are formed on semiconductor wafers at increasingly smaller scale. In current technology nodes, such as 7, 10 and 14 nanometer technologies, transistor devices are constructed as three-dimensional (3D) fin field effect transistor (FINFET) structures. The fins of the FINFETs are typically constructed as repeating, equally spaced, vertical structures on the wafer. Equally spaced gates are formed as repeating vertical structures that overlay the fins in an orthogonal direction.
A challenge in constructing the repeating structures such as fins and gates at, for instance, the 7 nanometer technology node, is the need for a larger/taller gate budget (e.g., 110 nm) as compared to previous technology nodes (e.g., 60 nm for 14LP) due to significant gate height loss during processing (e.g., >60 nm loss). However, such an increase in the gate budget (i.e., processing layer thicknesses) to combat gate height loss creates a new problem, namely high aspect ratios for trenching/cutting during processing. A method of forming a 7LP gate structure utilizing a smaller gate budget and having reduced aspect ratios is needed.
In addition, the 7 nanometer technology node typically suffers from “epi merge” (merging of epitaxially grown structures) when epitaxial films are deposited on the fins during subsequent processing due to decreased (and potentially unequal) spacing between fins. Thus, a method of forming a 7LP gate structure that avoids epi merge and therefore provides improved device performance is also needed.